1. Field of the Invention
The present invention relates to a latch circuit, and more specifically to a latch circuit having a logical operation function.
2. Description of Related Art
A latch circuit is one of fundamental circuits used in various electronic circuits including a memory, an arithmetic and logic unit, and others.
Referring to FIG. 1, there is shown a circuit diagram of a typical latch circuit in the prior art. The shown latch circuit includes an inverter 310 having an input receiving an input signal 302 through a transfer gate 320, which is controlled by a pair of complementary clock signals. CK 300 and CK 301. An output of the inverter 301 is connected to an input of another inverter 312, having an output for outputting an output signal 303. The output of the inverter 310 is also connected to an input of still another inverter 311. An output of the inverter 311 is connected to the input of the inverter 310 through another transfer gate 321, which is controlled by the pair of complementary clock signals CK 300 and CK 301.
This latch circuit operates as follows: When the clock signal CK 300 is at a low level L (and therefore the clock signal CK 301 is at a high level H), the transfer gate 320 is opened, namely turned on, and therefore, the input signal 302 pass through the inverters 310 and 312 to be outputted as the output signal 303.
When the clock signal CK is brought to a high level H, the transfer gate 320 is turned off, and the transfer gate 321 is turned on. As a result, a loop is formed of the inverters 310 and 311 so that the value of the output signal 303 just before the rising of the clock signal CK 300 is held.
Referring to FIG. 2, there is shown a circuit diagram of one example of an electronic circuit incorporating the prior art latch circuit shown in FIG. 1.
The shown electronic circuit includes first, second and third prior art latch circuits 410, 411 and 412, each of which is the same as that shown in FIG. 1, and is controlled by a pair of complementary clock signals CK 400 and CK 401. The first, second and third prior art latch circuits 410, 411 and 412 latch first, second and third input signals 402, 403 and 404, respectively. Outputs of the first, second and third prior art latch circuits 410, 411 and 412 are connected to three inputs of a three-input NAND gate circuit 440.
As well known to persons skilled in the art, if the NAND gate circuit 440 is formed of a CMOS circuit, it includes first, second and third N-channel MOS transistors 450, 451 and 452 connected in series between an output node 470 and ground, and first, second and third P-channel MOS transistors 460, 461 and 462 connected in parallel between a high voltage terminal VDD and the output node 470. Gates of the first N-channel MOS transistor 450 and the first P-channel MOS transistor 460 are connected to the output of the first prior art latch circuit 410, and gates of the second N-channel MOS transistor 451 and the second P-channel. MOS transistor 461 are connected to the output of the second prior art latch circuit 411. In addition, gates of the third N-channel MOS transistor 452 and the third P-channel MOS transistor 462 are connected to the output of the third prior art latch circuit 412.
When the clock signal CK 400 is at a low level, the first, second and third input signals 402, 403 and 404 pass through the first, second and third prior art latch circuits 410, 411 and 412, respectively, so that the first, second and third input signals 402, 403 and 404 are applied without modification to the inputs of the three-input NAND gate circuit 440, with the result that the NAND gate circuit 440 outputs an NAND (negated logical product) of the three input signals.
At the moment the clock signal CK 400 is brought to a high level, logical values of the three input signals are latched in the three latch circuits 410, 411 and 412, respectively. Accordingly, during a period in which the clock signal CK 400 is at the high level, the output of the three-input NAND gate circuit 440 continues to maintain the same logical value.
Here, it is to be noted that the above mentioned example is simply one example, and therefore, the output of the latch circuits may be connected to a two-input NAND gate circuit or may be connected to a NOR gate circuit. However, for simplification of the succeeding explanation, description will be made on a case that the output of the latch circuits may be connected to a three-input NAND gate circuit.
Referring to FIG. 3, there is shown a circuit diagram of a latch circuit with logical operation function, which corresponds in function to three latch circuits and a three-input NAND gate circuit connected thereto. In this specification, the latch circuit with the logical operation function shown in FIG. 3 will be called a "conventional latch circuit with logical operation function".
The shown latch circuit has a function of a three-input NAND circuit and a function of a latch circuit. First, second and third input signals 502, 503 and 504 am supplied to first, second and third inputs 505, 506 and 507 of a three-input NAND circuit 510 through first, second and third transfer gates 520, 521 and 522, respectively, which are controlled by a pair of complementary clock signals CK 500 and CK 501. An output 508 of the three-input NAND circuit 510 is connected to an input of a feedback inverter 511, which in rum has an output connected to the first, second and third inputs 505, 506 and 507 of the three-input NAND circuit 510 through fourth, fifth and sixth transfer gates 523,524 and 525, respectively. These fourth, fifth and sixth transfer gates 523, 524 and 525 are controlled by the pair of complementary clock signals CK 500 and CK 501 in such a manner that when the first, second and third transfer gates 520, 521 and 522 are opened or turned on, the fourth, fifth and sixth transfer gates 523, 524 and 525 are closed or turned off, and when the first, second and third transfer gates 520, 521 and 522 are closed or turned off, the fourth, fifth and sixth transfer gates 523, 524 and 525 are opened or turned on.
The three-input NAND circuit 510 is formed of first, second and third N-channel MOS transistors 550, 551 and 552 and first, second and third P-channel MOS transistors 560, 561 and 562, completely similarly to the three-input NAND circuit 410 shown in FIG. 2.
When the clock signal CK 500 is at a low level, the first, second and third input signals 502, 503 and 504 pass through the first, second and third transfer gates 520, 521 and 522 to be applied to the first, second and third inputs 505, 506 and 507 of the three-input NAND circuit 510, so that the three-input NAND circuit 510 outputs an NAND of the three input signals 502, 503 and 504.
When the clock signal CK 500 is brought to a high level, the first, second and third transfer gates 520, 521 and 522 are turned off, and the fourth, fifth and sixth transfer gates 523,524 and 525 are turned on. As a result, there is formed a feedback loop from the output 508 of the three-input NAND circuit 510 through the inverter 511 to the first, second and third inputs 505,506 and 507 of the three-input NAND circuit 510. Namely, an inverted signal of the output 508 of the three-input NAND circuit 510 is fed back to the first, second and third inputs 505, 506 and 507 of the three-input NAND circuit 510. Accordingly, the output of the three-input NAND circuit 510 is latched.
Thus, the NAND function at the outside of the latch circuits in the example shown in FIG. 2, is internally realized in the latch circuit. If the "conventional latch circuit with logical operation function" is used in place of the circuit construction shown in FIG. 2, the signal propagation time can be shortened by a delay time corresponding to the two inverter stages in the latch circuit (See JP-A-03-238914).
However, the "conventional latch circuit with logical operation function" has the following disadvantage: Here, consider a timing pattern as shown in FIG. 4.
Consider a situation that the first, second and third input signals change from "L, H, H" to "H, H, H" during a high level period (latched period) of the clock signal CK as shown in the timing chart shown in FIG. 4. First, during the high level period of the clock signal CK, the three-input NAND gate circuit 510 outputs a high level (H) as a negated logical product of "L, H, H". Therefore, all the N-channel MOS transistors 550, 551 and 552 of the three-input NAND gate circuit 510 are off. When the clock signal CK is brought to a low level (L), the three-input NAND gate circuit 510 outputs a low level output signal (L) in response to the first, second and third input signals change of "H, H, H". At this time, all the N-channel MOS transistors 550,551 and 552 of the three-input NAND gate circuit 510 are turned on.
On the other hand, also consider that a signal pattern shown in FIG. 4 is applied to the conventional latch and NAND gate circuit as shown in FIG. 2. When the clock signal CK 400 is at the high level (H), the first, second and third prior art latch circuits 410, 411 and 412 latch "L, H, H", respectively, in accordance with the first, second and third input signals of "L, H, H". At this time, the second and third N-channel MOS transistors 451 and 452 are on, and the first N-channel MOS transistor 450 is off. Therefore, when the clock signal CK 400 is brought to a low level. (L), the output of the first prior art latch circuit 410 changes from the low level (L) to the high level (H) in response to the first input signal of "H", so that the first N-channel MOS transistor 450 is turned on.
As seen from the above, in the circuit shown in FIG. 2, when the input signals change as shown in FIG. 4, since two of the three series-connected N-channel MOS transistors in the three-input NAND gate are already on, only one of the three series-connected N-channel MOS transistors is turned on. In the "conventional latch circuit with logical operation function" shown in FIG. 3, however, all the three series-connected N-channel MOS transistors in the three-input NAND gate are turned on. Accordingly, the NAND gate of FIG. 3 has a delay time longer than that of the NAND gate of FIG. 2. Therefore, the "conventional latch circuit with logical operation function" can eliminate the delay caused by the two cascaded inverters 310 and 312 included in the prior art latch circuit, but the operation speed of the NAND gate itself is low. Because of this, although the logical operation function is realized in the latch circuit, the operation cannot be sufficiently speeded up.